AD6677 datasheet(3/48 Pages) AD

3 / 48 page

Data Sheet

AD6677

Rev. C | Page 3 of 48

The NSR block can be programmed to provide a bandwidth of

either 22% or 33% of the sample clock. For example, with a

sample clock rate of 250 MSPS, the AD6677 can achieve up to

76.3 dBFS SNR for a 55 MHz bandwidth in the 22% mode and

up to 73.5 dBFS SNR for an 82 MHz bandwidth in the 33% mode.

When the NSR block is disabled, the ADC data is provided directly

to the output at a resolution of 11 bits. The AD6677 can achieve

up to 65.9 dBFS SNR for the entire Nyquist bandwidth when

operated in this mode. This allows the AD6677 to be used in

telecommunication applications such as a digital predistortion

observation path where wider bandwidths are required.

The output data is routed directly to an external JESD204B serial

output lane. This output is at current mode logic (CML) voltage

levels. Only one JESD204B lane configuration such that the output

coded data is sent through one lane (L = 1; F = 4). Synchronization

input controls (SYNCINB± and SYSREF±) are provided.

The AD6677 receiver digitizes a wide spectrum of IF frequencies.

This IF sampling architecture greatly reduces component cost and

complexity compared with traditional analog techniques or less

integrated digital methods.

Flexible power-down options allow significant power savings,

when desired. Programmable overrange level detection is

supported via dedicated fast detect pins.

Programming for setup and control is accomplished using a

3-wire SPI-compatible serial interface with numerous modes to

support board level system testing.

The AD6677 is available in a 32-lead LFCSP and is specified over

the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1. The configurable JESD204B output block with an integrated

phase-locked loop (PLL) to support lane rates up to 5 Gbps.

2. The IF receiver includes an 11-bit, 250 MSPS ADC with

programmable NSR function that allows for improved SNR

within a reduced bandwidth of 22% or 33% of the sample rate.

3. Support for an optional radio frequency (RF) clock input to

ease system board design.

4. Proprietary differential input maintains excellent SNR

performance for input frequencies of up to 400 MHz.

5. An on-chip integer, 1-to-8 input clock divider and SYNC

input allow synchronization of multiple devices.

6. Operation from a single 1.8 V power supply.

7. Standard SPI that supports various product features and

functions, such as controlling the clock DCS, power-down,

test modes, voltage reference mode, overrange fast

detection, and serial output configuration.

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