AD6677 datasheet(43/48 Pages) AD

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Data Sheet

AD6677

Rev. C | Page 43 of 48

Bit 4—Reserved

Bits[3:0]—JESD204B N’ Value

Read only bits showing the total number of bits per sample,

minus 1 (reads back 15 (0xF) for 16 bits per sample).

JESD204B Samples per Converter per Frame Cycle (S)

(Address 0x74)

Bits[7:6]—Open

Bit 5—Reserved; set to 1

Bits[4:0]—JESD204B samples per converter per frame cycle (S)

Read only bits showing the number of samples per converter

frame cycle, minus 1 (reads back 0 (0x0) for one sample per

converter frame).

JESD204B Parameters, HD and CF (Address 0x75)

Bit 7—JESD204B high density (HD) value (read only)

Read only bit. Always set to 0.

Bits[6:5]—Open

Bits[4:0]—JESD204B control words per frame clock cycle per

link (CF)

Read only bits. Reads back 0x0.

JESD204B Reserved 1 (Address 0x76)

Bits[7:0]—JESD204B Reserved Field 1

This read/write register is available for customer use.

JESD204B Reserved 2 (Address 0x77)

Bits[7:0]—JESD204B Reserved Field 2

This read/write register is available for customer use.

JESD204B Checksum (Address 0x79)

Bits[7:0]—JESD204B checksum value for the output lane

This read only register is automatically calculated for the lane.

Checksum equals sum (all link configuration parameters for the

lane) modulus 256.

JESD204B Output Driver Control (Address 0x80)

Bits[7:1]—Reserved

Bit 1—JESD204B driver power-down

When this bit is set low, the JESD204B output drivers are enabled.

When this bit is set high, the JESD204B output drivers are

powered down.

JESD204B LMFC Offset (Address 0x8B)

Bits[7:5]—Reserved

Bits[4:0]—Local multiframe clock phase offset value

These bits are the reset value for the local multiframe clock

(LMFC) phase counter when SYSREF± is asserted. These bits

are used in applications requiring deterministic delay.

JESD204B Preemphasis (Address 0xA8)

Bits[7:0]—JESD204B preemphasis enable option

These bits enable the preemphasis feature on the JESD204B

output drivers. Setting Bits[7:0] to 0x04 disables preemphasis,

and setting Bits[7:0] to 0x14 enables preemphasis.

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