AD6677 datasheet(40/48 Pages) AD

40 / 48 page

AD6677

Data Sheet

Rev. C | Page 40 of 48

MEMORY MAP REGISTER DESCRIPTIONS

For more information on functions controlled in Address 0x00 to

Address 0x21 and Address 0xFF, with the exception of Address 0x08

and Address 0x14, see the Application Note AN-877, Interfacing

to High Speed ADCs via SPI.

PDWN Modes (Address 0x08)

Bits[7:6]—Reserved

Bit 5—External PDWN mode

This bit controls the function of the PDWN pin. When this bit is 0,

asserting the PDWN pin results in a full power-down of the device.

When this bit is 1, asserting the PDWN pin places the device in

standby.

Bit 4—JESD204B standby mode

This bit controls the state of the JESD204B digital circuitry when

the external PDWN pin places the device into standby. If this

bit is 0, the JES204B digital circuitry is not placed into standby.

When this bit is 1, the JESD204B circuitry is placed into standby

when the PDWN pin is asserted and Bit 5 is 1.

Bits[3:2]—JESD204B power modes

These bits control the power modes of the JESD204B digital

circuitry. When Bits[3:2] = 00, the JESD204B digital circuitry

is in normal mode. When Bits[3:2] = 01, the JESD204B digital

circuitry is in power-down mode with the PLL off, serializer

off, clocks stopped, and the digital circuitry held in reset. When

Bits[3:2] = 10, the JESD204B digital circuitry is placed into

standby mode with the PLL on, serializer off, clocks stopped,

and the digital circuitry held in reset.

Bits[1:0]—ADC power modes

These bits select power mode for the ADC excluding the

JESD204B digital circuitry. When Bits[1:0] = 00, the ADC is in

normal mode. When Bits[1:0] = 01, the ADC is placed into power-

down mode, and when Bits[1:0] = 10, the ADC is placed into

standby mode.

Output Mode (Address 0x14)

Bits[7:5]—JESD204B CS bits assignment

These bits control the function of the CS bits in the JESD204B

serial data stream.

Bit 4—ADC output disable

If this bit is set, the output data from the ADC is disabled.

Bit 3—Open

Bit 2—ADC data invert

If this bit is set, the output data from the ADC is inverted.

Bits[1:0]—Data format select

These bits select the output data format. When Bits[1:0] = 00,

the output data is in offset binary format, and when Bits[1:0] = 01,

the output data is in twos complement format.

SYNCINB±/SYSREF± Control (Address 0x3A)

Bits[7:5]—Reserved

Bit 4—JESD204B realign SYNCINB±

When this bit is set low, the JESD204B link operates in normal

mode. When this bit is high, the JESD204B link realigns on

every active SYNCINB± assertion.

Bit 3—JESD204B realign SYSREF±

When this bit is set low, the JESD204B link operates in normal

mode. When this bit is high, the JESD204B link realigns on

every active SYSREF± assertion.

Bit 2—SYSREF± mode

When this bit is set low, the clock dividers are continuously reset on

each SYSREF± assertion. When this bit is high, the clock dividers

are reset on the next rising edge of SYSREF± only.

Bit 1—SYSREF± enable

When this bit is set low, the SYSREF± input is disabled. When

this bit is high, the SYSREF± input is enabled.

Bit 0—Enable SYNCINB± buffer

When this bit is set low, the SYNCINB± input buffer is disabled.

When this bit is high, the SYNCINB± input buffer is enabled.

NSR Control (Address 0x3C)

Bits[7:2]—Reserved

Bit 1—Bandwidth mode (NSR)

Bit 1 determines the bandwidth mode of the NSR. When Bit 1 is

set to 0, the NSR is configured for 22% bandwidth mode, which

provides enhanced SNR performance over 22% of the sample rate.

When Bit 1 is set to 1, the NSR is configured for 33% bandwidth

mode, which provides enhanced SNR performance over 33% of

the sample rate.

Bit 0—NSR enable

The NSR is enabled when Bit 0 is high and disabled when Bit 0

is low.

NSR Tuning Word (Address 0x3E)

Bits[7:6]—Reserved

Bits[5:0]—Noise shaped requantizer tuning word

The NSR tuning word sets the band edges of the NSR band. In

22% bandwidth mode, there are 57 possible tuning words, and

in 33% bandwidth mode, there are 34 possible tuning words. In

either mode, each step represents 0.5% of the ADC sample rate.

For the equations that calculate the tuning word based on the

bandwidth mode of operation, see the Noise Shaping

Requantizer section.

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