AD6677 datasheet(9/48 Pages) AD

9 / 48 page

Data Sheet

AD6677

Rev. C | Page 9 of 48

TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SPI TIMING REQUIREMENTS (See Figure 58)

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the SCLK

Setup time between CS and SCLK

Hold time between CS and SCLK

tHIGH

Minimum period that SCLK must be in a logic high state

tLOW

Minimum period that SCLK must be in a logic low state

tEN_SDIO

Time required for the SDIO pin to switch from an input to an

output relative to the SCLK falling edge (not shown in figures)

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge (not shown in figures)

tSPI_RST

Time required after hard or soft reset until SPI access is available

(not shown in figures)

500

µs

Timing Diagrams

N – 36

N – 35

N – 34

N – 33

N – 1

N + 1

SAMPLE N

ANALOG

INPUT

SIGNAL

CLK–

CLK+

CLK–

CLK+

SERDOUT0±

SAMPLE N – 36

ENCODED INTO 2

8B/10B SYMBOLS

SAMPLE N – 35

ENCODED INTO 2

8B/10B SYMBOLS

SAMPLE N – 34

ENCODED INTO 2

8B/10B SYMBOLS

Figure 2. Data Output Timing

tREFS

tREFH

tREFSRF

tREFHRF

RFCLK

CLK–

CLK+

SYSREF–

SYSREF+

NOTES

1. CLOCK INPUT IS EITHER RFCLK OR CLK±, NOT BOTH.

Figure 3. SYSREF± Setup and Hold Timing (Clock Input Either RFCLK or CLK±, Not Both)

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