HD6433636SW datasheet(243/418 Pages) RENESAS

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Serial Control Register 3 (SCR3)

Bit

76543210

TIE

RIE

MPIE

TEIE

CKE1

CKE0

Initial value

00000000

Read/Write

R/W

Serial control register 3 (SCR3) is an 8-bit register that controls SCI3 transmit and receive

operations, enables or disables serial clock output in asynchronous mode, enables or disables

interrupts, and selects the serial clock source. SCR3 can be read and written by the CPU at any

time.

SCR3 is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or

subsleep mode.

Bit 7—Transmit Interrupt Enable (TIE): Bit 7 enables or disables the transmit data empty

interrupt request (TXI) when data is transferred from TDR to TSR and the transmit data register

empty bit (TDRE) in the serial status register (SSR) is set to 1. The TXI interrupt can be cleared

by clearing bit TDRE to 0, or by clearing bit TIE to 0.

Bit 7: TIE

Description

Transmit data empty interrupt request (TXI) disabled

(initial value)

Transmit data empty interrupt request (TXI) enabled

Bit 6—Receive Interrupt Enable (RIE): Bit 6 enables or disables the receive error interrupt

request (ERI), and the receive data full interrupt request (RXI) when data is transferred from RSR

to RDR and the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1.

Receive errors include overrun errors, framing errors, and parity errors. RXI and ERI interrupts

can be cleared by clearing SSR flag RDRF, or flags FER, PER, and OER to 0, or by clearing bit

RIE to 0.

Bit 6: RIE

Description

Receive data full interrupt request (RXI) and receive error interrupt request

(ERI) disabled

(initial value)

Receive data full interrupt request (RXI) and receive error interrupt request

(ERI) enabled

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