HD6433636SW datasheet(245/418 Pages) RENESAS

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Bit 2—Transmit End Interrupt Enable (TEIE): Bit 2 enables or disables the transmit end

interrupt (TEI) requested if there is no valid transmit data in TDR when the MSB is transmitted.

Bit 2: TEIE

Description

Transmit end interrupt (TEI) disabled

(initial value)

Transmit end interrupt (TEI) enabled*

Note: * A TEI interrupt can be cleared by clearing the SSR bit TDRE to 0 and clearing the transmit

end bit (TEND) to 0, or by clearing bit TEIE to 0.

Bits 1 and 0—Clock Enable 1, 0 (CKE1, CKE0): Bits 1 and 0 select the clock source and enable

or disable clock output at pin SCK

3. The combination of bits CKE1 and CKE0 determines whether

pin SCK

3 is a general I/O port, a clock output pin, or a clock input pin.

Note that the CKE0 setting is valid only when operation is in asynchronous mode using an internal

clock (CKE1 = 0). This bit is invalid in synchronous mode or when using an external clock

(CKE1 = 1). In synchronous mode and in external clock mode, clear CKE0 to 0. After setting bits

CKE1 and CKE0, the operation mode must first be set in the serial mode register (SMR).

See table 10.10 in 10.3.3, Operation, for details on clock source selection.

Description

Bit 1: CKE1

Bit 0: CKE0

Communication Mode

Clock Source

SCK

3 Pin Function

Asynchronous

Internal clock

I/O port*1

Synchronous

Internal clock

Serial clock output*1

Asynchronous

Internal clock

Clock output*2

Synchronous

Reserved

Asynchronous

External clock

Clock input*3

Synchronous

External clock

Serial clock input

Asynchronous

Reserved

Synchronous

Reserved

Notes: 1. Initial value

2. A clock is output with the same frequency as the bit rate.

3. Input a clock with a frequency 16 times the bit rate.

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