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HD6433636SW Folha de dados(PDF) 230 Page - Renesas Technology Corp |
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HD6433636SW Folha de dados(HTML) 230 Page - Renesas Technology Corp |
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230 / 418 page ![]() 216 Bit 3—Clock Source Select 3 (CKS3): Bit 3 selects the clock source and sets pin SCK 1 as an input or output pin. Bit 3: CKS3 Description 0 Clock source is prescaler S, and pin SCK 1 is output pin (initial value) 1 Clock source is external clock, and pin SCK 1 is input pin Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS 0): When CKS3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle. Serial Clock Cycle Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Prescaler Division ø = 5 MHz ø = 2.5 MHz 0 0 0 ø/1024 (initial value) 204.8 µs 409.6 µs 1 ø/256 51.2 µs 102.4 µs 1 0 ø/64 12.8 µs 25.6 µs 1 ø/32 6.4 µs 12.8 µs 1 0 0 ø/16 3.2 µs 6.4 µs 1 ø/8 1.6 µs 3.2 µs 1 0 ø/4 0.8 µs 1.6 µs 1 ø/2 — 0.8 µs Serial Control/Status Register 1 (SCSR1) Bit 76543210 — SOL ORER ———— STF Initial value 10011100 Read/Write — R/W R/(W)* ——— R R/W Note: * Only a write of 0 for flag clearing is possible. SCSR1 is an 8-bit read/write register indicating operation status and error status. Upon reset, SCSR1 is initialized to H'9C. Do not read or write to SCSR1 during a transfer operation, as this will cause erroneous operation. Bit 7—Reserved Bit: Bit 7 is reserved; it is always read as 1, and cannot be modified. |
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