UCD3138064ARGCR.A datasheet(65/84 Pages) TI2

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3 A – QB1

( DPWM1C )

3 B – QT1

( DPWM2 C)

2 B – QB2

( EDGEGEN )

2 A – QT 2

( EDGEGEN)

0 B –

QSYN 2,4

1 B –

QSYN 1 ,3

Transformer

Voltage

X1 , X2 , X 3 and Y1 , Y2 , Y 3

are sets of moving edges

All other edges are fixed .

DPWM 2 AF

DPWM 2 BF

DPWM3 AF

DPWM3 BF

Current

Peak Level

UCD3138064A

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SLUSCA5B – DECEMBER 2015 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

Here is an overview of the key PSFB signals:

Figure 7-3. Key PSFB Signals

7.2.2.2.1 DPWM Synchronization

DPWM1 is synchronized to DPWM0, DPWM2 is synchronized to DPWM1, and DPWM3 is synchronized to

DPWM2, ½ period out of phase using these commands:

Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //configured to slave

Dpwm2Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave

Dpwm3Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave

Dpwm0Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;

Dpwm1Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;

Dpwm2Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;

LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL

= 0;

LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL

= 1;

LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL

= 2;

// Slave to dpwm-0

// Slave to dpwm-1

// Slave to dpwm-2

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