UCD3138064ARGCR.A datasheet(27/84 Pages) TI2

27 / 84 page

Start of Period

Period Counter

Start of Period

Period

Sample Trigger 1

DPWM Output A

Cycle Adjust A (High Resolution)

Event 2 (High Resolution)

Event 1

Event 3 (High Resolution)

Cycle Adjust B (High Resolution)

Event 4 (High Resolution)

DPWM Output B

Blanking A Begin

Blanking A End

Blanking B Begin

Blanking B End

Phase Trigger

Sample Trigger 2

To Other

Modules

To Other

Modules

Multi Mode Open Loop

Events which change with DPWM mode:

DPWM A Rising Edge = Event 1

DPWM A Falling Edge = Event 2 + Cycle Adjust A

DPWM B Rising Edge = Event 3

DPWM B Falling Edge = Event 4 + Cycle Adjust B

Phase Trigger = Phase Trigger Register value

Events always set by their registers, regardless of mode:

Sample Trigger 1, Sample Trigger 2, Blanking A Begin , Blanking A End , Blanking B Begin,

Blanking B End

UCD3138064A

www.ti.com

SLUSCA5B – DECEMBER 2015 – REVISED JANUARY 2017

Submit Documentation Feedback

Product Folder Links: UCD3138064A

Detailed Description

Figure 6-4. Multi Mode Open Loop

Figure 6-4 is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own

registers, not by the filter output. In other words, the power supply control loop is not closed.

The Sample Trigger signals are used to trigger the Front End to sample input signals. The Blanking

signals are used to blank fault measurements during noisy events, such as FET turn on and turn off.

Additional DPWM modes are described below.

UCD3138064ARGCR.A Folha de dados(PDF) 27 Page - Texas Instruments

UCD3138064ARGCR.A Folha de dados(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Folha de dados Download

Ligação URL