UCD3138064ARGCR.A datasheet(43/84 Pages) TI2

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tCSS

tWH

tWL

tCSH

tSU

VALID IN

VALID OUT

SCS

SCK

MISO

MOSI

tHO

PSCK

Period SCK

2 ICLK

tWH

SCK High Time

1/2 PSCK

tWL

SCK Low Time

1/2 PSCK

tSU

Data in setup

2 ns (typical)

Data in hold

4 ns (typical)

Ouput Valid

4 ns (typical)

tHO

Ouput Data Hold

2 ns (typical)

tCSS

Chip Select Setup

1 PSCK

tCSH

Chip Select Hold

1 PSCK

UCD3138064A

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SLUSCA5B – DECEMBER 2015 – REVISED JANUARY 2017

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Detailed Description

Figure 6-22. SPI Timing Diagram

6.4.8

Timers

External to the Digital Power Peripherals there are 3 different types of timers in UCD3138x. They are the

24-bit timer, 16-bit timer and the watchdog timer

6.4.8.1

24-Bit Timer

There is one 24 bit timer which runs off the Interface Clock. It can be used to measure the time between

two events, and to generate interrupts after a specific interval. Its clock can be divided down by an 8-bit

pre-scalar to provide longer intervals. The timer has two compare registers (Data Registers). Both can be

used to generate an interrupt after a time interval. . Additionally, the timer has a shadow register (Data

Buffer register) which can be used to store CPU updates of the compare events while still using the timer.

The selected shadow register update mode happens after the compare event matches.

The two capture pins TCAP0 and TCAP1 are inputs for recording a capture event. A capture event can be

set either to rising, falling, or both edges of the capture pin signal. Upon this event, the counter value is

stored in the corresponding capture data register. Five Interrupts from the 24 bit timer can be set, which

are the counter rollover event (overflow), capture events 0 and 1, and the two comparison match events.

Each interrupt can be disabled or enabled.

6.4.8.2

16-Bit PWM Timers

There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided

down by a 8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers

(Data Registers) for generating the PWM set/unset events. Additionally, each timer has a shadow register

(Data Buffer register) which can be used to store CPU updates of compare events while still using the

timer. The selected shadow register update mode happens after the compare event matches.

UCD3138064ARGCR.A Folha de dados(PDF) 43 Page - Texas Instruments

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