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UCD3138064ARGCR.A Folha de dados(PDF) 52 Page - Texas Instruments

Nome de Peças UCD3138064ARGCR.A
Descrição Electrónicos  UCD3138064A Highly Integrated Digital Controller for Isolated Power
PDF  84 Pages
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Fabricante Electrônico  TI2 [Texas Instruments]
Página de início  https://www.ti.com
Logo TI2 - Texas Instruments

UCD3138064ARGCR.A Folha de dados(HTML) 52 Page - Texas Instruments

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Start of Period
Period Counter
Start of Period
Period
DPWM Output A
Cycle Adjust A (High Resolution)
Filter Duty (High Resolution)
Event 1
To Other
Modules
Filter controlled edge
Event 3 (High Resolution)
Cycle Adjust B (High Resolution)
Filter Duty (High Resolution)
DPWM Output B
Blanking B Begin
Blanking B End
Phase Trigger
Sample Trigger 2
To Other
Modules
Sample Trigger 1
Blanking A Begin
Blanking A End
DTC Adjustment
DTC Adjustment
Adaptive Sample Trigger B
Adaptive Sample Trigger A
52
UCD3138064A
SLUSCA5B – DECEMBER 2015 – REVISED JANUARY 2017
www.ti.com
Submit Documentation Feedback
Product Folder Links: UCD3138064A
Detailed Description
Copyright © 2015–2017, Texas Instruments Incorporated
6.5.1.3
DPWM Multiple Output Mode
Multi mode is used for systems where each phase has only one driver signal. It enables each DPWM
peripheral to drive two phases with the same pulse width, but with a time offset between the phases, and
with different cycle adjusts for each phase.
The Multi-Mode diagram is shown in Figure 6-28.
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A + DTC Adjustment
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 3
DPWM B Falling Edge = Event 3 + Filter Duty + Cycle Adjust B + DTC Adjustment
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End,
Blanking B Begin, Blanking B End
Figure 6-28. DPWM Multi-Mode Closed Loop



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