UCD3138064ARGCR.A datasheet(36/84 Pages) TI2

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UCD3138064A

SLUSCA5B – DECEMBER 2015 – REVISED JANUARY 2017

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Detailed Description

3 = DPWMA(n) (Crossover)

4 = DPWMA(n+1)

5 = DPWMB(n+1)

6 = DPWMC(n+1)

7 = DPWMC(n+2)

8 = DPWMC(n+3)

The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply:

DPWM(n)

DPWM3

DPWM(n+1)

DPWM0

DPWM(n+2)

DPWM1

DPWM(n+3)

DPWM2

6.4.6

Filter

The UCD3138064A filter is a PID filter with many enhancements for power supply control. Some of its

features include:

•

Traditional PID Architecture

•

Programmable non-linear limits for automated modification of filter coefficients based on received

EADC error

•

Multiple coefficient sets fully configurable by firmware

•

Full 24-bit precision throughout filter calculations

•

Programmable clamps on integrator branch and filter output

•

Ability to load values into internal filter registers while system is running

•

Ability to stall calculations on any of the individual filter branches

•

Ability to turn off calculations on any of the individual filter branches

•

Duty cycle, resonant period, or phase shift generation based on filter output.

•

Flux balancing

•

Voltage feed forward

The first section of the filter is shown in Figure 6-14 :

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