UCD3138064ARGCR.A datasheet(63/84 Pages) TI2

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UCD3138064A

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SLUSCA5B – DECEMBER 2015 – REVISED JANUARY 2017

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Applications, Implementation, and Layout

7.2.1

Design Requirements

Table 7-2. Input Characteristics

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

ALL SPECIFICATIONS at Vin=400V and 25°C AMBIENT UNLESS OTHERWISE NOTED.

Vin

Input voltage range

Normal Operating

350

385

420

Vinmax

Max input voltage

Continuous

420

Iin

Input current

Vin=350V, Full Load

1.15

Istby

Input no load current

Output current is 0A

Von

Under voltage lockout

Vin Decreasing (input voltage is detected on secondary side)

340

Vhys

Vin Increasing

360

(1)

Ripple and noise are measured with 10µF Tantalum capacitor and 0.1µF ceramic capacitor across output.

Table 7-3. Output Characteristics

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

ALL SPECIFICATIONS at Vin=400V and 25°C AMBIENT UNLESS OTHERWISE NOTED.

Output voltage setpoint

No load on outputs

Regline

Line regulation

All outputs; 360

≤ Vin ≤ 420; IO = IOmax

0.5%

Regload

Load regulation

All outputs; 0

≤ IO ≤ IOmax; Vin = 400 V

Ripple and noise(1)

5Hz to 20 MHz

100

mVpp

Output current

Efficiency at phase-shift mode

Vo = 12 V, Io = 15 A

93%

Efficiency at PWM ZVS mode

Vo = 12 V, Io = 15 A

93%

Efficiency at hard switching mode

Vo = 12 V, Io = 15 A

90%

Vadj

Output adjust range

11.4

12.6

Vtr

Transient response

overshoot/undershoot

50% Load Step at 1AµS, min load at 2A

±0.36

tsettling

Transient response settling time

100

µS

tstart

Output rise time

10% to 90% of Vout

Overshoot

At Startup

Switching frequency

Over Vin and IO ranges

150

kHz

Ishare

Current sharing accuracy

50% - full load

±5%

Loop phase margin

10% - Full load

degree

Loop gain margin

10% - Full load

7.2.2

Detailed Design Procedure

7.2.2.1

PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration

Overview

The hardware configuration of the UCD3138x PCMC PSFB converter contains two critical elements that

are highlighted in the subsequent sections.

•

DPWM initialization - This section will highlight the key register settings and considerations necessary

for the UCD3138x to generate the correct MOSFET waveforms for this topology. This maintains the

proper phase relationship between the MOSFETs and synchronous rectifiers as well as the proper set

up required to function correctly with PCMC.

•

PCMC initialization - This section will discuss the register settings and hardware considerations

necessary to modulate the DPWM pins with PCMC and internal slope compensation.

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