UCD3138064ARGCR datasheet(71/83 Pages) TI1

71 / 83 page

EAP0

EAN0

DAC0

EADC

4 bit dithering gives 14 bits of effective resolution

97.65625 V/ LSB effective resolution

6 bit ADC

8mV/LSB

Signed 9 bit result

(error) 1 mV /LSB

AFE_GAIN

10 bit DAC

1. 5625mV/ LSB

Value

Dither

CPCC

Filter x

Ramp

SAR/ Prebias

Absolute Value

Calculation

Averaging

10 bit result

1.5625mV/LSB

3-AFE_GAIN

Peak Current Mode

Comparator

Peak Current

Detected

Differential to

Single Ended

AFE_GAIN

UCD3138064A

www.ti.com

SLUSCA5A – DECEMBER 2015 – REVISED AUGUST 2016

Submit Documentation Feedback

Product Folder Links: UCD3138064A

Applications, Implementation, and Layout

It may also be necessary to set a ramp ending value in the RAMPDACEND register.

In addition, it is necessary to set the D2S_COMP_EN bit in the EADCCTRL register. This is for enabling

the differential to single ended comparator function. The front end diagram leaves it out for simplicity, but

the connection between the DAC and the EADC amplifier is actually differential. The PCMC comparator,

however, is single ended. So a conversion is necessary as shown in Figure 7-9.

Figure 7-9. Differential to Single-Ended Comparator Function

The EADC_MODE bit in EADCCTRL should be set to a 5 for peak current mode.

The peak current detection signal next goes to the Loop Mux. The Fault Mux has only 1 APCM input, but

there are 3 front ends. So the PCM_FE_SEL bits in APCMCTRL must be used to select which front end is

used:

LoopMuxRegs.APCMCTRL.bit.PCM_FE_SEL = 2; // use FE2 for PCM */

The PCM_EN bit must also be set.

LoopMuxRegs.APCMCTRL.bit.PCM_EN = 1; // Enable PCM

Next the Fault Mux is used to enable the APCM bit to the CLIM/CBC signal to the DPWM. There are 4

DPWMxCLIM registers, one for each DPWM. The ANALOG_PCM_EN bit must be set in each one to

connect the PCM detection signal to the CLIM/CBC signal on each DPWM. For the latest configuration

information on all of these bits, consult the appropriate EVM firmware. To avoid errors, it is best to

configure your hardware design using the same DPWMs, filters, and front ends for the same functions as

the EVM.

DPWM timing is used to trigger the start of the ramp. This is selected by the FECTRLxMUX registers in

the Loop Mux. DPWMx_FRAME_SYNC_EN bits, when set, cause the ramp to be triggered at the start of

the DPWM period.

7.2.2.5.3 Peak Current Mode (PCM)

There is one peak current mode control module in the device however any front end can be configured to

use this module.

UCD3138064ARGCR Folha de dados(PDF) 71 Page - Texas Instruments

UCD3138064ARGCR Folha de dados(HTML) 71 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Folha de dados Download

Ligação URL