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UCD3138064ARGCR Folha de dados(PDF) 41 Page - Texas Instruments |
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UCD3138064ARGCR Folha de dados(HTML) 41 Page - Texas Instruments |
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41 / 83 page  Digital Comparator 0 Control Digital Comparator 1 Control Digital Comparator 2 Control Digital Comparator 3 Control Front End Control 0 Front End Control 1 Front End Control 2 Analog Comparator 0 Analog Comparator 0 Control Analog Comparator 1 Analog Comparator 1 Control Analog Comparator 2 Analog Comparator 2 Control Analog Comparator 3 Analog Comparator 3 Control Analog Comparator 4 Analog Comparator 4 Control Analog Comparator 5 Analog Comparator 5 Control Analog Comparator 6 Analog Comparator 6 Control External GPIO Detection fault[2:0] DPWM 0 DPWM 1 DPWM 2 DPWM 3 DPWM 0 Fault Control DPWM 1 Fault Control DPWM 2 Fault Control DPWM 3 Fault Control Analog Comparator Automated Ramp DCM Detection HFO/LFO Fail Detect 41 UCD3138064A www.ti.com SLUSCA5A – DECEMBER 2015 – REVISED AUGUST 2016 Submit Documentation Feedback Product Folder Links: UCD3138064A Detailed Description Copyright © 2015–2016, Texas Instruments Incorporated Figure 6-20. Fault Mux Block Diagram 6.4.7 Communication Ports 6.4.7.1 SCI (UART) Serial Communication Interface A maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous Receiver/Transmitter (UART) interfaces are included within the device for asynchronous start-stop serial data communication (see the pin out sections for details). Each interface has a 24 bit pre-scaler for supporting programmable baud rates, a programmable data word and stop bit options. Half or full duplex operation is configurable through register bits. A loop back feature can also be setup for firmware verification. Both SCI-TX and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being used. The UART peripheral includes a hardware based auto baud rate adjustment feature. Power supply controllers typically use temperature compensated RC based oscillators. Despite the temperature compensation, the clock speed will change with temperature. This can lead to a difference in baud rate between two controllers, leading to lost of communication. The UCD3138064A adds logic which can match the receive baud rate by measuring the bit timing of the incoming signal. In Addition, the UCD3138064A increases the resolution of the baud rate adjustment. The UCD3138064 has 512 ns resolution, while the UCD3138064A adds 3 bits and provides 64 ns resolution on the baud rate. This makes the use ot auto baud possible at higher baud rates. 6.4.7.2 PMBUS/I2C The PMBus interface in UCD3138064A supports both master and slave modes. The I2C interface only supports master mode. Only one of the interfaces has control of the address pin current sources as well as support for the optional Control and Alert lines described in the PMBus specification. Other than these differences, the interfaces are identical. |
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