UCD3138064ARGCR datasheet(22/83 Pages) TI1

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UCD3138064A

SLUSCA5A – DECEMBER 2015 – REVISED AUGUST 2016

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Detailed Description

6.4

Feature Description

6.4.1

System Module

The System Module contains the interface logic and configuration registers to control and configure all the

memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address

decoder, memory management controller, system management unit, central interrupt unit, and clock

control unit.

6.4.1.1

Address Decoder (DEC)

The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory

map addresses are selectable through configurable register settings. These memory selects can be

configured from 1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM

execution, which is then configured by the ROM code to the application setup. During access to the DEC

registers, a wait state is asserted to the CPU. DEC registers are only writable in the ARM privilege mode

for user mode protection.

6.4.1.2

Memory Management Controller (MMC)

The MMC manages the interface to the peripherals by controlling the interface bus for extending the read

and write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of

address space decoding.

6.4.1.3

System Management (SYS)

The SYS unit contains the software access protection by configuring user privilege levels to memory or

peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal

address or access conditions. A clock control setup for the processor clock (MCLK) speed, is also

available.

6.4.1.4

Central Interrupt Module (CIM)

The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor

supports two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides

hardware expansion of interrupts by use of FIQ/IRQ vector registers for providing the offset index in a

vector table. This numerical index value indicates the highest precedence channel with a pending interrupt

and is used to locate the interrupt vector address from the interrupt vector table. Interrupt channel 0 has

the lowest precedence and interrupt channel 31 has the highest precedence. To remove the interrupt

request, the firmware should clear the request as the first action in the interrupt service routine. The

request channels are maskable, allowing individual channels to be selectively disabled or enabled.

Table 6-1. Interrupt Priority Table

NAME

MODULE COMPONENT OR

DESCRIPTION

PRIORITY

BRN_OUT_INT

Brownout

Brownout interrupt

0 (Lowest)

EXT_INT

External Interrupts

Interrupt on external input pin

WDRST_INT

Watchdog Control

Interrupt from watchdog exceeded (reset)

WDWAKE_INT

Watchdog Control

Wake-up interrupt when watchdog equals half of set watch

time

SCI_ERR_INT

UART or SCI Control

UART or SCI error Interrupt. Frame, parity or overrun

SCI_RX_0_INT

UART or SCI Control

UART0 RX buffer has a byte

SCI_TX_0_INT

UART or SCI Control

UART0 TX buffer empty

SCI_RX_1_INT

UART or SCI Control

UART1 RX buffer has a byte

SCI_TX_1_INT

UART or SCI Control

UART1 TX buffer empty

PMBUS_INT

PMBus related interrupt

DIG_COMP_SPI_I2C_INT 12-bit ADC Control, SPI, I2C

Digital comparator, SPI and I2C interrupt

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