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UCD3138064ARGCR Folha de dados(PDF) 46 Page - Texas Instruments

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Nome de Peças UCD3138064ARGCR
Descrição Electrónicos  UCD3138064A Highly Integrated Digital Controller for Isolated Power
PDF  83 Pages
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Fabricante Electrônico  TI1 [Texas Instruments]
Página de início  http://www.ti.com
Logo TI1 - Texas Instruments

UCD3138064ARGCR Folha de dados(HTML) 46 Page - Texas Instruments

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UCD3138064A
SLUSCA5A – DECEMBER 2015 – REVISED AUGUST 2016
www.ti.com
Submit Documentation Feedback
Product Folder Links: UCD3138064A
Detailed Description
Copyright © 2015–2016, Texas Instruments Incorporated
GPIO functionality.
The Global I/O registers offer full control of:
1. Configuring each pin as a GPIO.
2. Setting each pin as input or output.
3. Reading the pin’s logic state, if it is configured as an input pin.
4. Setting the logic state of the pin, if it is configured as an output pin.
5. Connecting pin/pins to high rail through internal push/pull drivers or external pull up resistors.
The Global I/O registers include Global I/O EN register, Global I/O OE Register, Global I/O Open Drain
Control Register, Global I/O Value Register and Global I/O Read Register.
The following is showing the format of Global I/O EN Register (GLBIOEN) as an example:
BIT NUMBER
31:0
Bit Name
GLOBAL_IO_EN
Access
R/W
Default
0000_0000_0000_0000_0000_0000_0000_0000
Bits 29-0: GLOBAL_IO_EN – This register enables the global control of digital I/O pins
0 = Control of IO is done by the functional block assigned to the IO (Default)
1 = Control of IO is done by Global IO registers.
BIT
PIN_NAME
PIN NUMBER
UCD3138x
31
PWM2
11
30
PWM3
12
29
FAULT3
55
28
ADC_EXT_TRIG
14
27
TCK
45
26
TDO
46
25
TMS
48
24
TDI
47
23
SCI_TX1
37
22
SCI_TX0
35
21
SCI_RX1
38
20
SCI_RX0
36
19
TCAP0
49
18
PWM1
40
17
PWM0
39
16
TCAP1
13
15
I2C_DATA
20
14
PMBUS_CTRL
18
13
PMBUS_ALERT
17
12
EXT_INT
42
11
FAULT2
54
10
FAULT1
44
9
FAULT0
43
8
SYNC
34
7
DPWM3B
29
6
DPWM3A
28
5
DPWM2B
27
4
DPWM2A
26
3
DPWM1B
25



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