UCD3138064ARGCR datasheet(57/83 Pages) TI1

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UCD3138064A

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SLUSCA5A – DECEMBER 2015 – REVISED AUGUST 2016

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Detailed Description

6.6

Memory

6.6.1

6.6.1.1

CPU Memory Map and Interrupts

When the device comes out of power-on-reset, the data memories are mapped to the processor as

follows:

6.6.1.1.1 Memory Map (After Reset Operation)

Address

Size (Bytes)

Module

0x0000_0000 – 0x0003_FFFF

In 32 repeated blocks of 8 k each

32 X 8 k

Boot ROM

0x0004_0000 – 0x0004_7FFF

32 k

Program Flash 1

0x0004_8000 – 0x0004_FFFF

32 k

Program Flash 2

0x0006_8800 – 0x0006_8FFF

2 k

Data Flash

0x0006_9000 – 0x0006_9FFF

4 k

Data RAM

6.6.1.1.2 Memory Map (Normal Operation)

Just before the boot ROM program gives control to flash program, the ROM configures the memory as

follows:

Address

Size (Bytes)

Module

0x0000_0000 – 0x0000_7FFF

32 k

Program Flash 1 (or 2)

0x0000_8000 – 0x0000_FFFF

32 k

Program Flash 2 (or 1)

0x0002_0000 – 0x0002_1FFF

8 k

Boot ROM

0x0006_8800 – 0x0006_8FFF

2 k

Data Flash

0x0006_9000 – 0x0006_9FFF

4 k

Data RAM

6.6.1.1.3 Memory Map (System and Peripherals Blocks)

Address

Size

Module

0x0012_0000 - 0x0012_00FF

256

Loop Mux

0x0013_0000 - 0x0013_00FF

256

Fault Mux

0x0014_0000 - 0x0014_00FF

256

ADC

0x0015_0000 - 0x0015_00FF

256

DPWM 3

0x0016_0000 - 0x0016_00FF

256

Filter 2

0x0017_0000 - 0x0017_00FF

256

DPWM 2

0x0018_0000 - 0x0018_00FF

256

Front End/Ramp Interface 2

0x0019_0000 - 0x0019_00FF

256

Filter 1

0x001A_0000 - 0x001A_00FF

256

DPWM 1

0x001B_0000 – 0x001B_00FF

256

Front End/Ramp Interface 1

0x001C_0000 - 0x001C_00FF

256

Filter 0

0x001D_0000 - 0x001D_00FF

256

DPWM 0

0x001E_0000 - 0x001E_00FF

256

Front End/Ramp Interface 0

0xFFF7_EC00 - 0xFFF7_ECFF

256

UART 0

0xFFF7_ED00 - 0xFFF7_EDFF

256

UART 1

0xFFF7_F000 - 0xFFF7_F0FF

256

Miscellaneous Analog Control

0xFFF7_F600 - 0xFFF7_F6FF

256

PMBus Interface

0xFFF7_FA00 - 0xFFF7_FAFF

256

GIO

0xFFF7_FD00 - 0xFFF7_FDFF

256

Timer

0xFFFF_FD00 - 0xFFFF_FDFF

256

MMC

0xFFFF_FE00 - 0xFFFF_FEFF

256

DEC

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