UCD3138064ARGCR datasheet(28/83 Pages) TI1

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UCD3138064A

SLUSCA5A – DECEMBER 2015 – REVISED AUGUST 2016

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Detailed Description

6.4.2.1.4 High Resolution DPWM

Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of

PWM edges, the UCD3138x DPWM can generate waveforms with resolutions as small as 250 ps. This is

16 times the resolution of the clock driving the DPWM module.

This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz

each.

6.4.2.1.5 Over Sampling

The DPWM module has the capability to trigger an over sampling event by initiating the EADC to sample

the error voltage. The default “00” configuration has the DPWM trigger the EADC once based on the

sample trigger register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8

times per PWM period. Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the

sampling register. The “01” setting triggers 2X over sampling, the “10” setting triggers 4X over sampling,

and the “11” triggers over sampling at 8X.

6.4.2.1.6 DPWM Interrupt Generation

The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in

the period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower

interrupt service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12

trigger for sequence synchronization. Table 6-2 outlines the divide ratios that can be programmed.

6.4.2.1.7 DPWM Interrupt Scaling/Range

Table 6-2. DPWM Interrupt Divide Ratio

INTERRUPT

DIVIDE

SETTING

INTERRUPT

DIVIDE

COUNT

INTERRUPT

DIVIDE

COUNT (HEX)

SWITCHING PERIOD

FRAMES (assume

1MHz loop)

NUMBER OF 32

MHZ

PROCESSOR

CYCLES

128

256

512

1024

1536

2048

2560

3072

127

128

4096

159

160

5120

191

192

6144

223

224

7168

255

256

8192

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