UCD3138064ARGCR datasheet(68/83 Pages) TI1

Nome de Peças	UCD3138064ARGCR

Descrição Electrónicos	UCD3138064A Highly Integrated Digital Controller for Isolated Power

PDF	83 Pages

Scroll/Zoom	100%

Fabricante Electrônico	TI1 [Texas Instruments]

Página de início	http://www.ti.com

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2 B – QB2

( EDGEGEN )

2 A – QT 2

( EDGEGEN )

0 B –

QSYN 2,4

1 B –

QSYN 1,3

X1 , X2 , X 3 and Y 1 , Y2 , Y 3

are sets of moving edges

All other edges are fixed .

DPWM 2 AF

DPWM 2 BF

DPWM 3 AF

DPWM 3 BF

Current

Peak Level

3 A – QB1

( DPWM 1 C)

3 B – QT1

( DPWM 2 C)

Period Start

Period End

Chopping point

Y 1

UCD3138064A

SLUSCA5A – DECEMBER 2015 – REVISED AUGUST 2016

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Product Folder Links: UCD3138064A

Applications, Implementation, and Layout

Figure 7-6. Dynamic Signals to Bridge

The Edge Generator is configured with these statements:

Dpwm2Regs.DPWMEDGEGEN.bit.A_ON_EDGE = 2;

Dpwm2Regs.DPWMEDGEGEN.bit.A_OFF_EDGE = 5;

Dpwm2Regs.DPWMEDGEGEN.bit.B_ON_EDGE = 6;

Dpwm2Regs.DPWMEDGEGEN.bit.B_OFF_EDGE = 1;

Dpwm2Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 1; // EDGEGEN-A out the A output

Dpwm2Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 1; // EDGEGEN-B out the B output

Dpwm2Regs.DPWMEDGEGEN.bit.EDGE_EN = 1;

The EDGE_EN bits are set for all 4 DPWMs. This is done to ensure that all signals have the same timing

delay through the DPWM.

The final 6 gate signals are shown in Figure 7-7.

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