UCD3138064ARGCR datasheet(60/83 Pages) TI1

60 / 83 page

UCD3138064A

SLUSCA5A – DECEMBER 2015 – REVISED AUGUST 2016

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Detailed Description

6.6.1.5

Synchronous Rectifier MOSFET Ramp and IDE Calculation

The UCD3138064A has built in logic for optimizing the performance of the synchronous rectifier

MOSFETs. This comes in two forms:

•

Synchronous Rectifier MOSFET ramp

•

Ideal Diode Emulation (IDE) calculation

When starting up a power supply, It is not uncommon for there to already be a voltage present on the

output – this is called pre-bias. It can be very difficult to calculate the ideal synchronous rectifier MOSFET

on-time for this case. If it is not calculated correctly, it may pull down the pre-bias voltage, causing the

power supply to sink current. To avoid this, the synchronous rectifier MOSFETs are not turned on until

after the power supply has ramped up to the nominal output voltage. The synchronous rectifier MOSFETs

are then turned on slowly in order to avoid an output voltage glitch. The synchronous rectifier MOSFET

ramp logic can be used to turn them on at a rate well below the bandwidth of the filter.

In discontinuous mode, the ideal on-time for the synchronous rectifier MOSFETs is a function of Vin, Vout,

and the primary side duty cycle (D). The IDE logic in the UCD3138064A takes Vin and Vout data from the

firmware and combines it with D data from the filter hardware. It uses this information to calculate the ideal

on-time for the synchronous rectifier MOSFETs.

UCD3138064ARGCR Folha de dados(PDF) 60 Page - Texas Instruments