UCD3138064ARGCR datasheet(44/83 Pages) TI1

44 / 83 page

UCD3138064A

SLUSCA5A – DECEMBER 2015 – REVISED AUGUST 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: UCD3138064A

Detailed Description

The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a

software controlled register. Interrupts from the PWM timer can be set due to the counter rollover event

(overflow) or by the two comparison match events. Each comparison match and the overflow interrupts

can be disabled or enabled.

Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the

output. The value of PWM pin output can be read for status or simply configured as General Purpose I/O

for reading the value of the input at the pin.

6.4.8.3

Watchdog Timer

A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is

clocked off of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is

issued to the ARM processor. The watchdog is reset by a simple CPU write bit to the watchdog key

watchdog cannot be disabled by firmware. Only a device reset can put this bit back to the default disabled

state. A half timer flag is also provided for status monitoring of the watchdog.

6.4.9

General Purpose ADC12

The ADC12 is a 12 bit, high speed analog to digital converter, equipped with the following options:

•

Typical conversion speed of 267 ksps

•

Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence

•

Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples

•

Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge,

ADC_EXT_TRIG pin or Analog Comparator results

•

Interrupt capability to embedded processor at completion of ADC conversion

•

Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data

or averaged ADC data

•

Two 10 µA current sources for excitation of PMBus addressing resistors

•

Dual sample and hold for accurate power measurement

•

Internal temperature sensor for temperature protection and monitoring

The control module (Figure 6-23) contains the control and conversion logic for auto-sequencing a series of

conversions. The sequencing is fully configurable for any combination of 16 possible ADC channels

through an analog multiplexer embedded in the ADC12 block. Once converted, the selected channel value

is stored in the result register associated with the sequence number. Input channels can be sampled in

any desired order or programmed to repeat conversions on the same channel multiple times during a

conversion sequence. Selected channel conversions are also stored in the result registers in order of

conversion, where the result 0 register is the first conversion of a 16-channel sequence and result 15

sequence can vary from 1 to 16.

Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops,

the ADC12 is not usually used for loop compensation purposes. The EADC converters have a

substantially faster conversion rate, thus making them more attractive for closed loop control. The ADC12

features make it best suited for monitoring and detection of currents, voltages, temperatures and faults.

Please see Section 5.9 for the temperature variation associated with this function.

UCD3138064ARGCR Folha de dados(PDF) 44 Page - Texas Instruments

UCD3138064ARGCR Folha de dados(HTML) 44 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Folha de dados Download

Ligação URL