HD6433636SW datasheet(265/418 Pages) RENESAS

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SCI3 operates as follows during data transmission in asynchronous mode.

SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data

written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).

Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is

requested.

Serial data is transmitted from pin TXD using the communication format outlined in

table 10.14. After that, it checks TDRE at the same timing which it transmits the stop bit.

If TDRE is 0, data is transferred from TDR to TSR, and after the stop bit is sent, transmission of

the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the stop bit is sent,

the “mark state” is entered, in which 1 is continuously output. A TEI interrupt is requested in this

state if bit TEIE in SCR3 is set to 1.

Figure 10.9 shows a typical operation in asynchronous transmission mode.

0/1

Start

bit

Parity

bit

Stop

bit

Parity

bit

Stop

bit

Start

bit

Mark

state

TDRE

TEND

TXI request

TEI request

1 frame

TXI request

Serial

data

Transmit

data

Transmit

data

1 frame

SCI3

operation

User

processing

TDRE cleared to 0

Write data in TDR

Figure 10.9 Typical Transmit Operation in Asynchronous Mode

(8-Bit Data, Parity Bit Added, and 1 Stop Bit)

Receiving: Figure 10.10 shows a typical flow chart for receiving serial data. After SCI3

initialization, follow the procedure below.

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