HD6433636SW datasheet(224/418 Pages) RENESAS

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Bit 0—Watchdog Timer Reset (WRST): Bit 0 indicates that TCW has overflowed and an

internal reset signal has been generated. The internal reset signal generated by the overflow

resets the entire chip.

WRST is cleared by a reset via the

RES pin or by a 0 write by software.

Bit 0: WRST

Description

[Clearing conditions]

(initial value)

• Reset by RES pin

• When 0 is written to WRST while writing 0 to B0WI when TCSRWE is set

to 1

[Setting condition]

When TCW overflows and an internal reset signal is generated

Timer Counter W (TCW)

Bit

76543210

TCW7

TCW6

TCW5

TCW4

TCW3

TCW2

TCW1

TCW0

Initial value

00000000

Read/Write

R/W

Timer counter W (TCW) is an 8-bit read/write up-counter that is incremented by an input

internal clock. The input clock is ø/8192. The TCW value can be read or written by the CPU

at any time.

When TCW overflows (from H'FF to H'00), an internal reset signal is generated and WRST in

TCSRW is set to 1. Upon reset, TCW is initialized to H'00.

9.6.3

Operation

The watchdog timer is provided with an 8-bit timer that increments with each input clock

(ø/8192). If 1 is written to WDON while writing 0 to B2WI when TCSRWE in TCSRW is set

to 1, TCW begins counting up. When a clock pulse is input after the TCW count value has

reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The

internal reset signal is output for a period of 512 ø

osc clock cycles. TCW is a writable counter,

and when a value is set in TCW, the count-up starts from that value. An overflow period in

the range of 1 to 256 input clock cycles can therefore be set, according to the TCW value.

Figure 9.19 shows an example of watchdog timer operation.

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