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HD6433636SW Folha de dados(PDF) 219 Page - Renesas Technology Corp |
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HD6433636SW Folha de dados(HTML) 219 Page - Renesas Technology Corp |
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219 / 418 page ![]() 205 9.5.4 Operation Interval Timer Operation: When TMY7 in TMY is cleared to 0, timer Y operates as a 16- bit interval timer. In a reset, TCY is initialized to H'0000 and TMY7 is cleared to 0. Therefore, immediately after a reset, interval timer count-up continues. The timer Y operating clock can be selected with bits TMY2 to TMY0 in TMY from seven internal clocks output from prescaler S and the external clock from the TMCIY input pin. When a clock pulse is input after the TCY count value has reached H'FFFF, timer Y overflows and bit IRRTY in IRR1 is set to 1. If bit IENTY in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU.* When TCY overflows, the TCY count value returns to H'0000, and the count-up begins again from that value. When TLY is set in interval timer operation, the TLY value is simultaneously loaded into TCY. Note: * For details of the interrupt, see section 3.3, Interrupts. Auto-Reload Timer Operation: When TMY7 in TMY is set to 1, timer Y operates as a 16- bit auto-reload timer. When a reload value is set in TLY, it is simultaneously loaded into TCY, and TCY starts counting up from that value. When a clock pulse is input after the TCY count value has reached H'FFFF, timer Y overflows, the TLY value is loaded into TCY, and the count-up continues from that value. An overflow period in the range of 1 to 65,536 input clock cycles can therefore be set, according to the TLY value. The clock and interrupt conditions in auto-reload operation are the same as in interval operation. When the TLY is set again in auto-reload operation, the TLY value is simultaneously loaded into TCY. Event Counter: Timer Y operates as an event counter using the TMCIY pin as the event input pin. When TMY2 to TMY0 in TMY are set to 111, external event operation is selected, and TCY counts up on the rising/falling edges of TMCIY pin input. When external event input is used, bit IEN2 in IENR1 should be cleared to 0 to disable IRQ 2 interrupt requests. |
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