ADIN1101CCPZ-R7 datasheet(22/79 Pages) AD

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Data Sheet

ADIN1101

HARDWARE CONFIGURATION PINS

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Rev. A | 22 of 79

Table 19. Transmit Amplitude Selection (Hardware Configuration)

TX2P4_EN

Transmit Amplitude Selection

1.0 V p-p and 2.4 V p-p

1.0 V p-p

The TX2P4_EN hardware configuration pin signal configures

the value of the 10BASE-T1L high voltage transmit ability bit

(B10L_TX_LVL_HI_ABLE).

If TX2P4_EN is pulled low during power-up, hardware reset, or

software reset, the 2.4 V p-p transmit operating mode is enabled

and the value of B10L_TX_LVL_HI_ABLE is 1.

If TX2P4_EN is pulled high during power-up, hardware reset, or

software reset, the 2.4 V p-p transmit operating mode is disabled,

and the value of B10L_TX_LVL_HI_ABLE is 0.

The B10L_TX_LVL_HI_ABLE bit reports whether the PHY is capa-

ble of operating in the 10BASE-T1L high transmit voltage mode, as

described in Table 20.

Table 20. B10L_TX_LVL_HI_ABLE Settings

Bit Setting

Description

PHY does not support 10BASE-T1L high voltage (2.4 V p-p)

transmit level operating mode.

PHY supports 10BASE-T1L high voltage (2.4 V p-p) transmit

level operating mode.

MAC Interface Selection

The MAC interface hardware configuration pin signals (MA-

CIF_SELx) are shared with the RX_CLK/RXC and RX_ER signals

and can be configured according to Table 21. The RX_CLK/RXC/

MACIF_SEL0 and RX_ER/MACIF_SEL1 pins have weak internal

pull-down resistors. Thus, by default, the ADIN1101 is configured in

RMII mode. External pull-up/pull-down resistors or host control via

a GPIO must be used to select the RGMII or MII MAC interface

mode.

Table 21. MAC Interface Selection (Hardware Configuration)

MACIF_SEL1

MACIF_SEL0

MAC Interface Selection

RMII

RGMII

Reserved

MII

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