ADIN1101CCPZ-R7 datasheet(4/79 Pages) AD

4 / 79 page

Data Sheet

ADIN1101

SPECIFICATIONS

analog.com

Rev. A | 4 of 79

Table 1. General Specifications (Continued)

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK25_REF Clock Output

CLK25_REF Frequency

MHz

VOH

1.05

Load = 10 pF

VOL

Load = 10 pF

CLK25_REF Duty Cycle

Load = 10 pF

Long-Term Jitter (RMS)

1 Load capacitance (CL) = ((C1 × C2)/(C1 + C2) + CSTRAY), where CSTRAY is the stray capacitance including routing and package parasitics.

2 RP and CP are the values of the equivalent parallel RC circuit to ac ground (RP||CP), modeling the driving point impedance of the XTAL_I/CLK_IN pin.

Table 2. 10BASE-T1L Specifications

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER REQUIREMENTS

Supply Voltage Range

AVDD_H

3.13

3.3

3.46

2.4 V p-p or 1.0 V p-p transmit level

AVDD_L

1.71

1.8 or 3.3

3.46

AVDD_H, AVDD_L

1.71

1.8

3.46

1.0 V p-p transmit level

VDDIO

1.71

1.8, 2.5, or 3.3

3.46

1.0 V p-p Transmit Level (Single Supply)

AVDD_H = AVDD_L = VDDIO = 1.8 V

AVDD_x Supply Current, IAVDD

Power Consumption

100% data throughput, full activity

Software power-down mode

2.4 V p-p Transmit Level (Single Supply)

AVDD_H = AVDD_L = VDDIO = 3.3 V

Supply Current, IAVDD

Power Consumption

109

100% data throughput, full activity

Software power-down mode

2.4 V p-p Transmit Level (Dual Supply)

AVDD_H = 3.3 V, AVDD_L = VDDIO = 1.8 V

AVDD_x Supply Current, IAVDD

16.5

VDDIO Supply Current, IVDDIO

Power Consumption

100% data throughput, full activity

Software power-down mode

TIMING AND LATENCY

MII Latency

Transmit Latency

<1.8

μs

18-bit times

Receiver Latency

<3.2

μs

32-bit times

Total Latency

≤5

μs

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