ADIN1101CCPZ-R7 datasheet(76/79 Pages) AD

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Data Sheet

ADIN1101

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Rev. A | 76 of 79

Table 140. Bit Descriptions for FG_IFG_LEN

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_IFG_LEN

Frame Generator Interframe Gap Length. This register specifies the length in bytes of the interframe gap to be

inserted between frames by the frame generator.

0xC

R/W

Frame Generator Number of Frames High Register

Device Address: 0x1F; Register Address: 0x8027, Reset: 0x0000, Name: FG_NFRM_H

This register is Bits[31:16] of a 32-bit register that specifies the number of frames to be generated each time the frame generator is enabled or

restarted.

Table 141. Bit Descriptions for FG_NFRM_H

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_NFRM_H

Bits[31:16] of the Number of Frames to be Generated.

0x0

R/W

Frame Generator Number of Frames Low Register

Device Address: 0x1F; Register Address: 0x8028, Reset: 0x0100, Name: FG_NFRM_L

This register is Bits[15:0] of a 32-bit register that specifies the number of frames to be generated each time the frame generator is enabled or

restarted.

Table 142. Bit Descriptions for FG_NFRM_L

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_NFRM_L

Bits[15:0] of the Number of Frames to be Generated.

0x100

R/W

Frame Generator Done Register

Device Address: 0x1F; Register Address: 0x8029, Reset: 0x0000, Name: FG_DONE

This register is used to indicate that the frame generator completed the generation of the number of frames requested in the FG_NFRM_H and

FG_NFRM_L registers.

Table 143. Bit Descriptions for FG_DONE

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FG_DONE

Frame Generator Done. This bit reads as 1 to indicate that the generation of frames has completed. When set,

this bit goes high and it latches high until its unlatched by reading.

0x0

R LH

RMII Configuration Register

Device Address: 0x1F; Register Address: 0x8050, Reset: 0x0006, Name: RMII_CFG

Table 144. Bit Descriptions for RMII_CFG

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x3

RMII_TXD_CHK_EN

RMII TXD Check Enable. This bit determines whether or not TXD_1 to TXD_0 are monitored to

detect the start of a frame. This bit allows the RMII receiver CRS_DV signal to be connected to the

RMII TX_EN signal. This bit is mainly intended for debug and test purposes.

0x0

R/W

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