ADIN1101CCPZ-R7 datasheet(64/79 Pages) AD

64 / 79 page

Data Sheet

ADIN1101

analog.com

Rev. A | 64 of 79

Software Reset Register

Device Address: 0x1E; Register Address: 0x8810, Reset: 0x0000, Name: CRSM_SFT_RST

Table 99. Bit Descriptions for CRSM_SFT_RST

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

CRSM_SFT_RST

Software Reset Register. The software reset bit allows the chip to be reset. When this bit is set, the chip

fully initializes, almost equivalent to a hardware reset.

0x0

R/W SC

Software Power-Down Control Register

Device Address: 0x1E; Register Address: 0x8812, Reset: 0x0000, Name: CRSM_SFT_PD_CNTRL

Table 100. Bit Descriptions for CRSM_SFT_PD_CNTRL

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

CRSM_SFT_PD

Software Power-Down. The software power-down register puts the chip in a lower power mode.

In this mode, most of the circuitry is switched off. However, MDIO access to all registers is still

possible. The default value for this register is configurable via the RX_DV/SWPD_EN pin. This

pin allows the chip to be held in power-down mode until an appropriate software initialization is

performed.

Pin dependent

R/W

PHY Subsystem Reset Register

Device Address: 0x1E; Register Address: 0x8814, Reset: 0x0000, Name: CRSM_PHY_SUBSYS_RST

Table 101. Bit Descriptions for CRSM_PHY_SUBSYS_RST

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

CRSM_PHY_SUBSYS_RST

PHY Subsystem Reset. The PHY subsystem reset register allows a managed subsystem

reset to be initiated. When the PHY subsystem is reset, normal operation resumes, and the

bit self clears.

0x0

R/W SC

PHY MAC Interface Reset Register

Device Address: 0x1E; Register Address: 0x8815, Reset: 0x0000, Name: CRSM_MAC_IF_RST

Table 102. Bit Descriptions for CRSM_MAC_IF_RST

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

CRSM_MAC_IF_RST

PHY MAC Interface Reset. The PHY MAC interface reset register allows a managed PHY MAC

interface reset to be initiated. When the PHY MAC interface is reset, normal operation resumes, and

the bit self clears.

0x0

R/W SC

System Status Register

Device Address: 0x1E; Register Address: 0x8818, Reset: 0x0000, Name: CRSM_STAT

Table 103. Bit Descriptions for CRSM_STAT

Bits

Bit Name

Description

Reset

Access

[15:2]

RESERVED

Reserved.

0x0

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