ADIN1101CCPZ-R7 datasheet(11/79 Pages) AD

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Data Sheet

ADIN1101

THEORY OF OPERATION

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Rev. A | 11 of 79

The ADIN1101 is a low power, single port 10BASE-T1L Ethernet

PHY device, compliant with the IEEE 802.3cg Ethernet standard for

long reach, 10 Mbps single pair Ethernet.

The ADIN1101 integrates the following features:

►

PHY core with common analog circuitry

►

Input and output clock buffering

►

MDIO interface to control subsystem registers, clock, and soft-

ware resets

►

MAC interface control logic

►

Hardware configuration pins

►

Configurable hardware interrupt pin

►

Two configurable LED pins

POWER SUPPLY DOMAINS

The ADIN1101 has three power supply domains and requires a

minimum of one supply rail.

►

AVDD_H is the analog power supply input for the analog front

end (AFE) circuitry in the ADIN1101.

►

AVDD_L is the analog supply voltage for the internal LDO cir-

cuits. AVDD_L can be connected to the AVDD_H rail in single-

supply mode or to an alternative lower voltage rail in dual-supply

mode for lower power consumption.

►

VDDIO is the digital power supply input for the ADIN1101 MAC

interface, MDIO, and digital inputs/outputs (I/Os). VDDIO can be

connected directly to the AVDD_L rail or to an external power

rail.

The System Level Power Management section describes various

application circuits that can be used as reference.

In a single-supply application, connect AVDD_H = AVDD_L =

VDDIO. The appropriate supply voltage used depends on the end

application and cable length. The higher transmit amplitude of

2.4 V p-p requires AVDD_H = 3.3 V, whereas the lower transmit

amplitude of 1.0 V p-p requires AVDD_H = 1.8 V or 3.3 V.

MAC INTERFACE

The ADIN1101 provides the option of MII, RMII, or RGMII MAC

interfaces. The MAC interface is selected using the hardware

configuration pins (RX_CLK/RXC/MACIF_SEL0 and RX_ER/MA-

CIF_SEL1) or via the management interface (MDIO). The two

hardware configuration pins for MAC interface selection strap the

ADIN1101 configuration after power-up, hardware reset, or software

reset.

By default (hardware configuration pins floating), the MAC interface

is configured in RMII mode. See the MAC Interface Selection for

more details on how to configure the MAC interface using the

hardware configuration pins.

It is recommended to use the hardware configuration pins for the

MAC interface selection because the supported interfaces have

different clock and pin mapping requirements.

MII Mode

For the receive MII, the ADIN1101 generates a 2.5 MHz reference

clock on RX_CLK to synchronize the RXD_3 to RXD_0 receive

data signals. RX_DV indicates to the MAC that valid data is present

on the RXD_3 to RXD_0 signals. RX_ER is driven high by the

ADIN1101 if an error was detected in the frame that was received

from the MDI interface and is being transmitted to the MAC inter-

face.

For the transmit MII, the ADIN1101 generates a 2.5 MHz reference

clock on TX_CLK. The MAC transmits data on TXD_3 to TXD_0

that is synchronized with TX_CLK. The MAC asserts TX_EN high to

indicate to the ADIN1101 that transmission data is available on the

TXD_3 to TXD_0 signal lines.

Figure 10. MII MAC PHY Interface Signals

RMII Mode

RMII mode requires an external 50 MHz clock, which can be

sourced externally from a MAC chip or a reference clock and

applied to the ADIN1101 XTAL_I/CLK_IN pin. The 50 MHz clock is

used for both the transmit and receive interfaces.

The receive data, RXD_1 to RXD_0, transitions synchronously to

the reference clock (REF_CLK). The carrier sense and received

data valid signal (CRS_DV) is a combination of the carrier sense

and RX_DV signals, and is asserted while the receive medium is

not idle. CRS_DV is asserted asynchronously to REF_CLK and

deasserted synchronously.

RX_ER is also synchronous to the reference clock signal

(REF_CLK) and asserted when an error is detected in the received

frame or when a false carrier is detected. RX_ER assertion on a

false carrier can be disabled by software.

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