ADIN1101CCPZ-R7 datasheet(72/79 Pages) AD

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Data Sheet

ADIN1101

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Rev. A | 72 of 79

Receive Error Count Register

Device Address: 0x1F; Register Address: 0x8008, Reset: 0x0000, Name: RX_ERR_CNT

The receive error counter register is used to access the receive error counter associated with the frame checker in the PHY.

Table 124. Bit Descriptions for RX_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

RX_ERR_CNT

Receive Error Count. This bit is the receive error counter associated with the frame checker in the PHY. Note

that this bit is self clearing upon reading.

0x0

R SC

Frame Checker Count High Register

Device Address: 0x1F; Register Address: 0x8009, Reset: 0x0000, Name: FC_FRM_CNT_H

This register is a latched copy of Bits[31:16] of the 32-bit of the receive frame counter register. When the receive error counter (RX_ERR_CNT)

is read, the receive frame counter register is latched so that the error count and the receive frame count are synchronized.

Table 125. Bit Descriptions for FC_FRM_CNT_H

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_FRM_CNT_H

Bits[31:16] of Latched Copy of the Number of Received Frames.

0x0

Frame Checker Count Low Register

Device Address: 0x1F; Register Address: 0x800A, Reset: 0x0000, Name: FC_FRM_CNT_L

This register is a latched copy of Bits[15:0] of the 32-bit receive frame counter register. When the receive error counter (RX_ERR_CNT) is read,

the receive frame counter register is latched so that the error count and receive frame count are synchronized.

Table 126. Bit Descriptions for FC_FRM_CNT_L

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_FRM_CNT_L

Bits[15:0] of Latched Copy of the Number of Received Frames.

0x0

Frame Checker Length Error Count Register

Device Address: 0x1F; Register Address: 0x800B, Reset: 0x0000, Name: FC_LEN_ERR_CNT

This register is a latched copy of the frame length error counter register. This register is a count of received frames with a length error status.

When the receive error counter (RX_ERR_CNT) is read, the frame length error counter register is latched, which ensures that the frame length

error count and receive frame count are synchronized.

Table 127. Bit Descriptions for FC_LEN_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_LEN_ERR_CNT

Latched Copy of the Frame Length Error Counter.

0x0

Frame Checker Alignment Error Count Register

Device Address: 0x1F; Register Address: 0x800C, Reset: 0x0000, Name: FC_ALGN_ERR_CNT

This register is a latched copy of the frame alignment error counter register. This register is a count of received frames with an alignment error

status. When the receive error counter (RX_ERR_CNT) is read, the alignment error counter is latched, which ensures that the frame alignment

error count and the receive frame count are synchronized.

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