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MPC8360CVVALFHA Folha de dados(PDF) 14 Page - Freescale Semiconductor, Inc |
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MPC8360CVVALFHA Folha de dados(HTML) 14 Page - Freescale Semiconductor, Inc |
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14 / 102 page  MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5 14 Freescale Semiconductor Power Sequencing This table shows the estimated typical I/O power dissipation for the device. 4 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8360E/58E. NOTE The rise/fall time on QUICC Engine block input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from 10% to 90% of VDD; fall time refers to transitions from 90% to 10% of VDD. Table 6. Estimated Typical I/O Power Dissipation Interface Parameter GVDD (1.8 V) GVDD (2.5 V) OVDD (3.3 V) LVDD (3.3 V) LVDD (2.5 V) Unit Comments DDR I/O 65% utilization Rs = 20 Ω Rt = 50 Ω 2 pairs of clocks 200 MHz, 1 × 32 bits 0.3 0.46 — — — W — 200 MHz, 1 × 64 bits 0.4 0.58 — — — W — 200 MHz, 2 × 32 bits 0.6 0.92 — — — W — 266 MHz, 1 × 32 bits 0.35 0.56 — — — W — 266 MHz, 1 × 64 bits 0.46 0.7 — — — W — 266 MHz, 2 × 32 bits 0.7 1.11 — — — W — 333 MHz, 1 × 32 bits 0.4 0.65 — — — W — 333 MHz, 1 × 64 bits 0.53 0.82 — — — W — 333 MHz, 2 × 32 bits 0.81 1.3 — — — W — Local Bus I/O Load = 25 pf 3 pairs of clocks 133 MHz, 32 bits — — 0.22 — — W — 83 MHz, 32 bits — — 0.14 — — W — 66 MHz, 32 bits — — 0.12 — — W — 50 MHz, 32 bits — — 0.09 — — W — PCI I/O Load = 30 pF 33 MHz, 32 bits — — 0.05 — — W — 66 MHz, 32 bits — — 0.07 — — W — 10/100/1000 Ethernet I/O Load = 20 pF MII or RMII — — — 0.01 — W Multiply by number of interfaces used. GMII or TBI — — — 0.04 — W RGMII or RTBI ———— 0.04 W Other I/O — — — 0.1 — — W — |
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