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MPC8360CVVALFHA Folha de dados(PDF) 85 Page - Freescale Semiconductor, Inc |
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MPC8360CVVALFHA Folha de dados(HTML) 85 Page - Freescale Semiconductor, Inc |
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85 / 102 page ![]() MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5 Freescale Semiconductor 85 System PLL Configuration Low 0110 6:1 100 150 200 Low 0111 7:1 116 175 233 Low 1000 8:1 133 200 266 Low 1001 9:1 150 225 300 Low 1010 10:1 166 250 333 Low 1011 11:1 183 275 Low 1100 12:1 200 300 Low 1101 13:1 216 325 Low 1110 14:1 233 Low 1111 15:1 250 Low 0000 16:1 266 High 0010 2:1 133 High 0011 3:1 100 200 High 0100 4:1 133 266 High 0101 5:1 166 333 High 0110 6:1 200 High 0111 7:1 233 High 1000 8:1 High 1001 9:1 High 1010 10:1 High 1011 11:1 High 1100 12:1 High 1101 13:1 High 1110 14:1 High 1111 15:1 High 0000 16:1 1 CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be pulled down (low) in agent mode. 2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. Table 72. CSB Frequency Options (continued) CFG_CLKIN_DIV at Reset1 SPMF csb_clk: Input Clock Ratio2 Input Clock Frequency (MHz)2 16.67 25 33.33 66.67 csb_clk Frequency (MHz) |
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