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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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MPC8360CVVALFHA Folha de dados(PDF) 60 Page - Freescale Semiconductor, Inc |
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MPC8360CVVALFHA Folha de dados(HTML) 60 Page - Freescale Semiconductor, Inc |
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60 / 102 page  MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5 60 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART AC Timing Specifications This figure provides the AC test load. Figure 49. AC Test Load Outputs—Internal clock high impedance tHIKHOX -0.5 5.5 ns Outputs—External clock high impedance tHEKHOX 18 ns Inputs—Internal clock input setup time tHIIVKH 8.5 — ns Inputs—External clock input setup time tHEIVKH 4— ns Inputs—Internal clock input hold time tHIIXKH 1.4 — ns Inputs—External clock input hold time tHEIXKH 1— ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Table 63. Synchronous UART AC Timing Specifications1 Characteristic Symbol2 Min Max Unit Outputs—Internal clock delay tUAIKHOV 011.3 ns Outputs—External clock delay tUAEKHOV 114 ns Outputs—Internal clock high impedance tUAIKHOX 011 ns Outputs—External clock high impedance tUAEKHOX 114 ns Inputs—Internal clock input setup time tUAIIVKH 6— ns Inputs—External clock input setup time tUAEIVKH 8— ns Inputs—Internal clock input hold time tUAIIXKH 1— ns Inputs—External clock input hold time tUAEIXKH 1— ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Table 62. HDLC, BISYNC, and Transparent AC Timing Specifications1 (continued) Characteristic Symbol2 Min Max Unit Output Z0 = 50 Ω OVDD/2 RL = 50 Ω |
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