MPC8360CVVALFHA datasheet(12/102 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

Power Sequencing

2.2.1

Power-Up Sequencing

MPC8360E/58E does not require the core supply voltage (VDD and AVDD) and I/O supply voltages (GVDD, LVDD, and OVDD)

to be applied in any particular order. During the power ramp up, before the power supplies are stable and if the I/O voltages are

supplied before the core voltage, there may be a period of time that all input and output pins are actively be driven and cause

contention and excessive current from 3A to 5A. In order to avoid actively driving the I/O pins and to eliminate excessive current

draw, apply the core voltage (VDD) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the power

supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal

value before the I/O supplies reach 0.7 V, see this figure.

Figure 5. Power Sequencing Example

I/O voltage supplies (GVDD, LVDD, and OVDD) do not have any ordering requirements with respect to one another.

2.2.2

Power-Down Sequencing

The MPC8360E/58E does not require the core supply voltage and I/O supply voltages to be powered down in any particular

order.

Power Characteristics

The estimated typical power dissipation values are shown in these tables.

Table 4. MPC8360E TBGA Core Power Dissipation1

Core

Frequency (MHz)

CSB

Frequency (MHz)

QUICC Engine

Frequency (MHz)

Typical

Maximum

Unit

Notes

266

500

5.0

5.6

2, 3, 5

400

266

400

4.5

5.0

2, 3, 4

533

266

400

4.8

5.3

2, 3, 4

667

333

400

5.8

6.3

3, 6, 7, 8

500

333

500

5.9

6.4

3, 6, 7, 8

I/O Voltage (GVDD, LVDD, OVDD)

Core Voltage (VDD, AVDD)

90%

0.7 V

Time

Voltage

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