MPC8360CVVALFHA datasheet(96/102 Pages) FREESCALE

96 / 102 page

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

System Clocking

22.3.1

Experimental Determination of the Junction Temperature with a

Heat Sink

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case

of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of

the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to

the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature

and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this

case temperature, the junction temperature is determined from the junction-to-case thermal resistance.

TJ = TC + (RθJC × PD)

where:

TJ = junction temperature (° C)

TC = case temperature of the package (° C)

RθJC = junction to case thermal resistance (° C/W)

PD = power dissipation (W)

System Design Information

This section provides electrical and thermal design recommendations for successful application of the MPC8360E/58E.

Additional information can be found in MPC8360E/MPC8358E PowerQUICC Design Checklist (AN3097).

23.1

System Clocking

The device includes two PLLs, as follows.

•

The platform PLL (AVDD1) generates the platform clock from the externally supplied CLKIN input. The frequency

ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in

Section 21.1, “System PLL Configuration.”

•

The e300 core PLL (AVDD2) generates the core clock as a slave to the platform clock. The frequency ratio between

the e300 core clock and the platform clock is selected using the e300 PLL ratio configuration bits as described in

Section 21.2, “Core PLL Configuration.”

23.2

PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1, AVDD2, respectively).

The AVDD level should always be equivalent to VDD, and preferably these voltages are derived directly from VDD through a

low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide five independent

filter circuits as illustrated in Figure 56, one to each of the five AVDD pins. By providing independent filters to each PLL, the

opportunity to cause noise injection from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built

with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.

Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors

of equal value are recommended over a single large value capacitor.

Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from

nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of package,

without the inductance of vias.

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