MPC8360CVVALFHA datasheet(55/102 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

SPI AC Timing Specifications

This figure provides the AC test load for the SPI.

Figure 41. SPI AC Test Load

These figures represent the AC timing from Table 56. Note that although the specifications generally reference the rising edge

of the clock, these AC timing diagrams also apply when the falling edge is the active edge.

This figure shows the SPI timing in slave mode (external clock).

Figure 42. SPI AC Timing in Slave Mode (External Clock) Diagram

This figure shows the SPI timing in Master mode (internal clock).

Figure 43. SPI AC Timing in Master Mode (Internal Clock) Diagram

SPI inputs—Slave mode (external clock) input hold time

tNEIXKH

2—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI

outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are

valid (V).

Table 56. SPI AC Timing Specifications1

Characteristic

Symbol2

Min

Max

Unit

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

SPICLK (Input)

tNEIXKH

tNEIVKH

tNEKHOV

Input Signals:

SPIMOSI

(See Note)

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

SPICLK (Output)

tNIIXKH

tNIKHOV

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

tNIIVKH

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