MPC8360CVVALFHA datasheet(84/102 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

System PLL Configuration

The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in this table.

NOTE

The VCO divider must be set properly so that the system VCO frequency is in the range of

600–1400 MHz.

The system VCO frequency is derived from the following equations:

•

csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF

•

System VCO Frequency = csb_clk × VCO divider (if both RCWL[DDRCM] and RCWL[LBCM] are cleared)

•

System VCO frequency = 2

× csb_clk × VCO divider (if either RCWL[DDRCM] or RCWL[LBCM] are set).

As described in Section 21, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset configuration word low and

the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input (CLKIN or PCI_CLK) and

the internal coherent system bus clock (csb_clk). This table shows the expected frequency values for the CSB frequency for

select csb_clk to CLKIN/PCI_SYNC_IN ratios.

1100

× 12

1101

× 13

1110

× 14

1111

× 15

Table 71. System PLL VCO Divider

RCWL[SVCOD]

VCO Divider

Reserved

Table 72. CSB Frequency Options

CFG_CLKIN_DIV

at Reset1

SPMF

csb_clk:

Input Clock Ratio2

Input Clock Frequency (MHz)2

16.67

33.33

66.67

csb_clk Frequency (MHz)

Low

0010

2:1

133

Low

0011

3:1

100

200

Low

0100

4:1

100

133

266

Low

0101

5:1

125

166

333

Table 70. System PLL Multiplication Factors (continued)

RCWL[SPMF]

System PLL

Multiplication Factor

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