MPC8360CVVALFHA datasheet(79/102 Pages) FREESCALE

79 / 102 page

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

Pinout Listings

No Connect

AM16, AM17, AM20, AN13, AN16, AN17, AP10,

AP11, AP13, AP15, AP18, AR11, AR13, AR14,

AR15, AR16, AR17, AR20, AT11, AT12, AT13,

AT14, AT16, AT17, AT18, AU10, AU11, AU12,

AU13, AU15, AU19

——

—

Notes:

1. This pin is an open drain signal. A weak pull-up resistor (1 k

Ω) should be placed on this pin to OVDD.

2. This pin is an open drain signal. A weak pull-up resistor (2–10 k

Ω) should be placed on this pin to OVDD.

3. This output is actively driven during reset rather than being three-stated during reset.

4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.

6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance.

7. This pin must always be tied to GND.

8. This pin must always be left not connected.

9. Refer to MPC8360E PowerQUICC II Pro Integrated Communications Processor Reference Manual section on “RGMII Pins,”

for information about the two UCC2 Ethernet interface options.

10.This pin must always be tied to GVDD.

11.It is recommended that MDIC0 be tied to GND using an 18.2

Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω

resistor for DDR2.

Table 67. MPC8358E TBGA Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power

Supply

Notes

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