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MPC8360CVVALFHA Folha de dados(PDF) 86 Page - Freescale Semiconductor, Inc

Nome de Peças MPC8360CVVALFHA
Descrição Electrónicos  PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications
PDF  102 Pages
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Fabricante Electrônico  FREESCALE [Freescale Semiconductor, Inc]
Página de início  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8360CVVALFHA Folha de dados(HTML) 86 Page - Freescale Semiconductor, Inc

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
86
Freescale Semiconductor
Core PLL Configuration
21.2
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock
(core_clk). This table shows the encodings for RCWL[COREPLL]. COREPLL values not listed in this table should be
considered reserved.
NOTE
Core VCO frequency = Core frequency × VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]) must be set properly so that the core VCO frequency is in the
range of 800–1800 MHz. Having a core frequency below the CSB frequency is not a
possible option because the core frequency must be equal to or greater than the CSB
frequency.
Table 73. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk:csb_clk
Ratio
VCO divider
0–1
2–5
6
nn
0000
n
PLL bypassed
(PLL off, csb_clk
clocks core directly)
PLL bypassed
(PLL off, csb_clk
clocks core directly)
00
0001
01:1
÷2
01
0001
01:1
÷4
10
0001
01:1
÷8
11
0001
01:1
÷8
00
0001
11.5:1
÷2
01
0001
11.5:1
÷4
10
0001
11.5:1
÷8
11
0001
11.5:1
÷8
00
0010
02:1
÷2
01
0010
02:1
÷4
10
0010
02:1
÷8
11
0010
02:1
÷8
00
0010
12.5:1
÷2
01
0010
12.5:1
÷4
10
0010
12.5:1
÷8
11
0010
12.5:1
÷8
00
0011
03:1
÷2
01
0011
03:1
÷4
10
0011
03:1
÷8
11
0011
03:1
÷8



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