HD6433636SW datasheet(255/418 Pages) RENESAS

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Table 10.10 Relation between n and Clock

SMR Setting

Clock

CKS1

CKS0

0ø

ø/4

ø16

ø/64

10.3.3

Operation

SCI3 supports serial data communication in both asynchronous mode, where each character

transferred is synchronized separately, and synchronous mode, where transfer is synchronized by

clock pulses.

The choice of asynchronous mode or synchronous mode, and the communication format, is made

in the serial mode register (SMR), as shown in table 10.11. The SCI3 clock source is determined

by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3), as shown in

table 10.12.

Asynchronous Mode:

• Data length: choice of 7 bits or 8 bits

• Choice for the addition of a parity bit, the multiprocessor bit as well as one or two stop bits

(these options determine the transmit/receive format and the character length).

• Framing error (FER), parity error (PER), overrun error (OER), and break signal can be

detected when data is received.

• Clock source: Choice of internal clocks or an external clock

 When an internal clock is selected: Operates on baud rate generator clock. A clock can be

output with the same frequency as the bit rate.

 When an external clock is selected: A clock input with a frequency 16 times the bit rate is

required (internal baud rate generator is not used).

Synchronous Mode:

• Transfer format: 8 bits

• Overrun errors can be detected when data is received.

• Clock source: Choice of internal clocks or an external clock

 When an internal clock is selected: Operates on baud rate generator clock, and outputs a

serial clock.

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