DSPIC30F6010_06 datasheet(146/222 Pages) MICROCHIP

146 / 222 page

dsPIC30F6010

DS70119E-page 144

If the oscillator has a very slow start-up time coming

out of POR, BOR or Sleep, it is possible that the

PWRT timer will expire before the oscillator has

started. In such cases, the FSCM will be activated and

the FSCM will initiate a clock failure trap, and the

COSC<1:0> bits are loaded with FRC oscillator selec-

tion. This will effectively shut-off the original oscillator

that was trying to start.

The user may detect this situation and restart the

oscillator in the clock fail trap ISR.

Upon a clock failure detection, the FSCM module will

initiate a clock switch to the FRC Oscillator as follows:

The COSC bits (OSCCON<13:12>) are loaded

with the FRC Oscillator selection value.

CF bit is set (OSCCON<3>).

OSWEN control bit (OSCCON<0>) is cleared.

For the purpose of clock switching, the clock sources

are sectioned into four groups:

Primary

Secondary

Internal FRC

Internal LPRC

The user can switch between these functional groups,

but cannot switch between options within a group. If the

primary group is selected, then the choice within the

group is always determined by the FPR<3:0> Configu-

ration bits.

The OSCCON register holds the Control and Status

bits related to clock switching.

• COSC<1:0>: Read only status bits always reflect

the current oscillator group in effect.

• NOSC<1:0>: Control bits which are written to

indicate the new oscillator group of choice.

- On POR and BOR, COSC<1:0> and

NOSC<1:0> are both loaded with the

Configuration bit values FOS<1:0>.

• LOCK: The LOCK status bit indicates a PLL lock.

• CF: Read only status bit indicating if a clock fail

detect has occurred.

• OSWEN: Control bit changes from a ‘0’ to a ‘1’

when a clock transition sequence is initiated.

Clearing the OSWEN control bit will abort a clock

transition in progress (used for hang-up

situations).

If Configuration bits FCKSM<1:0> = 1x, then the clock

switching and fail-safe clock monitor functions are

disabled. This is the default Configuration bit setting.

If clock switching is disabled, then the FOS<1:0> and

FPR<3:0> bits directly control the oscillator selection

and the COSC<1:0> bits do not control the clock

selection. However, these bits will reflect the clock

source selection.

21.2.8

PROTECTION AGAINST

ACCIDENTAL WRITES TO OSCCON

A write to the OSCCON register is intentionally made

difficult because it controls clock switching and clock

scaling.

To write to the OSCCON low byte, the following code

sequence must be executed without any other

instructions in between:

• Byte Write “0x46” to OSCCON low

• Byte Write “0x57” to OSCCON low

Byte Write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

To write to the OSCCON high byte, the following

instructions must be executed without any other

instructions in between:

• Byte Write “0x78” to OSCCON high

• Byte Write “0x9A” to OSCCON high

Byte Write is allowed for one instruction cycle. Write the

desired value or use bit manipulation instruction.

Note:

The application should not attempt to

switch to a clock of frequency lower than

100 KHz when the fail-safe clock monitor is

enabled.

such

clock

switching

performed, the device may generate an

oscillator fail trap and switch to the Fast RC

oscillator.

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