DSPIC30F6010_06 datasheet(39/222 Pages) MICROCHIP

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DS70119E-page 37

dsPIC30F6010

5.0

INTERRUPTS

The dsPIC30F6010 has 44 interrupt sources and 4

processor exceptions (traps), which must be arbitrated

based on a priority scheme.

The CPU is responsible for reading the Interrupt Vec-

tor Table (IVT) and transferring the address contained

in the interrupt vector to the program counter. The

interrupt vector is transferred from the program data

bus into the program counter, via a 24-bit wide

multiplexer on the input of the program counter.

The Interrupt Vector Table (IVT) and Alternate Inter-

rupt Vector Table (AIVT) are placed near the beginning

of program memory (0x000004). The IVT and AIVT

are shown in Figure 5-1.

The

interrupt

controller

responsible

for

pre-

processing the interrupts and processor exceptions,

prior to their being presented to the processor core.

The peripheral interrupts and traps are enabled, priori-

tized and controlled using centralized special function

registers:

• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>

All interrupt request flags are maintained in these

three registers. The flags are set by their respec-

tive peripherals or external signals, and they are

cleared via software.

• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>

All Interrupt Enable Control bits are maintained in

these three registers. These control bits are used

to individually enable interrupts from the

peripherals or external signals.

• IPC0<15:0>... IPC11<7:0>

The user assignable priority level associated with

each of these 44 interrupts is held centrally in

these twelve registers.

• IPL<3:0> The current CPU priority level is explic-

itly stored in the IPL bits. IPL<3> is present in the

CORCON register, whereas IPL<2:0> are present

in the status register (SR) in the processor core.

• INTCON1<15:0>, INTCON2<15:0>

Global interrupt control functions are derived from

these two registers. INTCON1 contains the con-

trol and status flags for the processor exceptions.

The INTCON2 register controls the external inter-

rupt request signal behavior and the use of the

alternate vector table.

All interrupt sources can be user assigned to one of

seven priority levels, 1 through 7, via the IPCx

registers. Each interrupt source is associated with an

interrupt vector, as shown in Table 5-1. Levels 7 and 1

represent the highest and lowest maskable priorities,

respectively.

If the NSTDIS bit (INTCON1<15>) is set, nesting of

interrupts is prevented. Thus, if an interrupt is currently

being serviced, processing of a new interrupt is pre-

vented, even if the new interrupt is of higher priority

than the one currently being serviced.

Certain interrupts have specialized control bits for

features like edge or level triggered interrupts, inter-

rupt-on-change, etc. Control of these features remains

within the peripheral module which generates the

interrupt.

The DISI instruction can be used to disable the

processing of interrupts of priorities 6 and lower for a

certain number of instructions, during which the DISI bit

(INTCON2<14>) remains set.

When an interrupt is serviced, the PC is loaded with the

address stored in the vector location in Program Mem-

ory that corresponds to the interrupt. There are 63 dif-

ferent vectors within the IVT (refer to Figure 5-2). These

vectors are contained in locations 0x000004 through

0x0000FE of program memory (refer to Figure 5-2).

These locations contain 24-bit addresses, and in order

to preserve robustness, an address error trap will take

place should the PC attempt to fetch any of these

words during normal execution. This prevents execu-

tion of random data as a result of accidentally decre-

menting a PC into vector space, accidentally mapping

a data space address into vector space, or the PC roll-

ing over to 0x000000 after reaching the end of imple-

mented program memory space. Execution of a GOTO

instruction to this vector space will also generate an

address error trap.

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046). For more information on the device

instruction set and programming, refer to the “dsPIC30F/

33F Programmer’s Reference Manual” (DS70157).

Note:

Interrupt Flag bits get set when an inter-

rupt condition occurs, regardless of the

state of its corresponding Enable bit. User

software should ensure the appropriate

Interrupt Flag bits are clear prior to

enabling an interrupt.

Note:

Assigning a priority level of 0 to an inter-

rupt source is equivalent to disabling that

interrupt.

Note:

The IPL bits become read-only whenever

the NSTDIS bit has been set to ‘1’.

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