DSPIC30F6010_06 datasheet(84/222 Pages) MICROCHIP

Nome de Peças	DSPIC30F6010

Descrição Electrónicos	High-Performance, 16-Bit Digital Signal Controllers

PDF	222 Pages

Scroll/Zoom	100%

Fabricante Electrônico	MICROCHIP [Microchip Technology]

Página de início	http://www.microchip.com

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84 / 222 page

dsPIC30F6010

DS70119E-page 82

14.7.2

TIMER OPERATION DURING CPU

IDLE MODE

When the CPU is placed in the Idle mode and the QEI

module is configured in the 16-bit Timer mode, the

16-bit

timer

will

operate

the

QEISIDL

bit

(QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon

executing POR and BOR. For halting the timer module

during the CPU Idle mode, QEISIDL should be set

to ‘1’.

If the QEISIDL bit is cleared, the timer will function

normally, as if the CPU Idle mode had not been

entered.

14.8

Quadrature Encoder Interface

Interrupts

The quadrature encoder interface has the ability to

generate an interrupt on occurrence of the following

events:

• Interrupt on 16-bit up/down position counter

rollover/underflow

• Detection of qualified index pulse, or if CNTERR

bit is set

• Timer period match event (overflow/underflow)

• Gate accumulation event

The QEI Interrupt Flag bit, QEIIF, is asserted upon

occurrence of any of the above events. The QEIIF bit

must be cleared in software. QEIIF is located in the

IFS2 Status register.

Enabling an interrupt is accomplished via the respec-

tive Enable bit, QEIIE. The QEIIE bit is located in the

IEC2 Control register.

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