DSPIC30F6010_06 datasheet(40/222 Pages) MICROCHIP

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dsPIC30F6010

DS70119E-page 38

5.1

Interrupt Priority

The user assignable Interrupt Priority (IP<2:0>) bits for

each individual interrupt source are located in the Least

Significant 3 bits of each nibble, within the IPCx regis-

ter(s). Bit 3 of each nibble is not used and is read as a

‘0’. These bits define the priority level assigned to a

particular interrupt by the user.

Since more than one interrupt request source may be

assigned to a specific user specified priority level, a

means is provided to assign priority within a given level.

This method is called “Natural Order Priority”.

Natural Order Priority is determined by the position of

an interrupt in the vector table, and only affects

interrupt operation when multiple interrupts with the

same user-assigned priority become pending at the

same time.

Table 5-1 lists the interrupt numbers and interrupt

sources for the dsPIC DSC devices and their

associated vector numbers.

The ability for the user to assign every interrupt to one

of seven priority levels implies that the user can assign

a very high overall priority level to an interrupt with a

low natural order priority. For example, the PLVD (Low-

Voltage Detect) can be given a priority of 7. The INT0

(external interrupt 0) may be assigned to priority level

1, thus giving it a very low effective priority.

TABLE 5-1:

INTERRUPT VECTOR TABLE

Note:

The user selectable priority levels start at

0, as the lowest priority, and level 7, as the

highest priority.

Note 1: The natural order priority scheme has 0

as the highest priority and 53 as the

lowest priority.

2: The natural order priority number is the

same as the INT number.

INT

Number

Vector

Number

Interrupt Source

Highest Natural Order Priority

INT0 – External Interrupt 0

IC1 – Input Capture 1

OC1 – Output Compare 1

T1 – Timer 1

IC2 – Input Capture 2

OC2 – Output Compare 2

T2 – Timer 2

T3 – Timer 3

SPI1

U1RX – UART1 Receiver

U1TX – UART1 Transmitter

ADC – ADC Convert Done

NVM – NVM Write Complete

SI2C – I2C™ Slave Interrupt

MI2C – I2C Master Interrupt

Input Change Interrupt

INT1 – External Interrupt 1

IC7 – Input Capture 7

IC8 – Input Capture 8

OC3 – Output Compare 3

OC4 – Output Compare 4

T4 – Timer 4

T5 – Timer 5

INT2 – External Interrupt 2

U2RX – UART2 Receiver

U2TX – UART2 Transmitter

SPI2

C1 – Combined IRQ for CAN1

IC3 – Input Capture 3

IC4 – Input Capture 4

IC5 – Input Capture 5

IC6 – Input Capture 6

OC5 – Output Compare 5

OC6 – Output Compare 6

OC7 – Output Compare 7

OC8 – Output Compare 8

INT3 – External Interrupt 3

INT4 – External Interrupt 4

C2 – Combined IRQ for CAN2

PWM – PWM Period Match

QEI – QEI Interrupt

Reserved

LVD – Low-Voltage Detect

FLTA – PWM Fault A

FLTB – PWM Fault B

45-53

53-61

Reserved

Lowest Natural Order Priority

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