HD64F2149YV datasheet(658/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 630 of 1044

REJ09B0280-0300

SIRQCR1 Bit 5—HIRQ9 Interrupt Enable 3 (IRQ9E3): Enables or disables a HIRQ9 interrupt

request when OBF3A is set by an ODR3 write.

Bit 5

IRQ9E3

Description

HIRQ9 interrupt request by OBF3A and IRQ9E3 is disabled

(Initial value)

[Clearing conditions]

• Writing 0 to IRQ9E3

• LPC hardware reset, LPC software reset

• Clearing OBF3A to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ9 interrupt request by setting OBF3A to 1 is enabled

[When IEDIR = 1]

HIRQ9 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ9E3 = 0

SIRQCR1 Bit 4—HIRQ6 Interrupt Enable 3 (IRQ6E3): Enables or disables a HIRQ6 interrupt

request when OBF3A is set by an ODR3 write.

Bit 4

IRQ6E3

Description

HIRQ6 interrupt request by OBF3A and IRQ6E3 is disabled

(Initial value)

[Clearing conditions]

• Writing 0 to IRQ6E3

• LPC hardware reset, LPC software reset

• Clearing OBF3A to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ6 interrupt request by setting OBF3A to 1 is enabled

[When IEDIR = 1]

HIRQ6 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ6E3 = 0

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