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HD64F2149YV Folha de dados(PDF) 662 Page - Renesas Technology Corp

Nome de Peças HD64F2149YV
Descrição Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
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HD64F2149YV Folha de dados(HTML) 662 Page - Renesas Technology Corp

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Section 18B Host Interface LPC Interface (LPC)
Rev. 3.00 Jan 18, 2006 page 634 of 1044
REJ09B0280-0300
SIRQCR0 Bit 0—HIRQ1 Interrupt Enable 1 (IRQ1E1): Enables or disables a HIRQ1 interrupt
request when OBF1 is set by an ODR1 write.
Bit 0
IRQ1E1
Description
0
HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled
(Initial value)
[Clearing conditions]
• Writing 0 to IRQ1E1
• LPC hardware reset, LPC software reset
• Clearing OBF1 to 0
1
HIRQ1 interrupt request by setting OBF1 to 1 is enabled
[Setting condition]
• Writing 1 after reading IRQ1E1 = 0
18B.2.10 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH
MSTPCRL
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP0 bit is set to 1, the host interface (HIF: LPC) halts and enters module stop mode.
See section 24.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.



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