HD64F2149YV datasheet(89/1075 Pages) RENESAS

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Section 2 CPU

Rev. 3.00 Jan 18, 2006 page 61 of 1044

REJ09B0280-0300

2.6.5

Notes on Use of Bit-Manipulation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit

manipulation, then write back the byte of data. Caution is therefore required when using these

instructions on a register containing write-only bits, or a port.

The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant

flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling

routine, etc.

2.7

Addressing Modes and Effective Address Calculation

2.7.1

Addressing Mode

The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of

these addressing modes. Arithmetic and logic instructions can use the register direct and

immediate modes. Data transfer instructions can use all addressing modes except program-counter

relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or

absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and

BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2.4

Addressing Modes

No.

Addressing Mode

Symbol

@ERn

@(d:16,ERn)/@(d:32,ERn)

@ERn+

@–ERn

Absolute address

@aa:8/@aa:16/@aa:24/@aa:32

Immediate

#xx:8/#xx:16/#xx:32

Program-counter relative

@(d:8,PC)/@(d:16,PC)

Memory indirect

@@aa:8

general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit

registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified

as 32-bit registers.

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