HD64F2149YV datasheet(87/1075 Pages) RENESAS

87 / 1075 page

Section 2 CPU

Rev. 3.00 Jan 18, 2006 page 59 of 1044

REJ09B0280-0300

Type

Instruction

Size*

Function

System

control

instructions

STC

B/W

CCR

→ (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or

memory. Although CCR and EXR are 8-bit registers,

word-size transfers are performed between them and

memory. The upper 8 bits are valid.

ANDC

CCR

∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with

immediate data.

ORC

CCR

∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate

data.

XORC

CCR

⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with

immediate data.

NOP

—

PC + 2

→ PC

Only increments the program counter.

Block data

transfer

instructions

EEPMOV.B

EEPMOV.W

—

if R4L

≠ 0 then

Repeat @ER5+

→ @ER6+

R4L–1

→ R4L

Until R4L = 0

else next;

if R4

≠ 0 then

Repeat @ER5+

→ @ER6+

R4–1

→ R4

Until R4 = 0

else next;

Block transfer instruction. Transfers the number of data

bytes specified by R4L or R4 from locations starting at

the address indicated by ER5 to locations starting at the

address indicated by ER6. After the transfer, the next

instruction is executed.

Notes: 1. Size refers to the operand size.

Byte

W: Word

Longword

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.

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