HD64F2149YV datasheet(655/1075 Pages) RENESAS

655 / 1075 page

Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 627 of 1044

REJ09B0280-0300

• SIRQCR1

Bit

543

210

IRQ11E3 IRQ10E3 IRQ9E3 IRQ6E3 IRQ11E2 IRQ10E2 IRQ9E2 IRQ6E2

Initial value

000

Slave Read/Write

R/W

Host Read/Write

——

———

The SIRQCR registers contain status bits that indicate the SERIRQ operating mode and bits that

specify SERIRQ interrupt sources.

The SIRQCR registers are initialized to H'00 by a reset and in hardware standby mode.

SIRQCR0 Bit 7—Quiet/Continuous Mode Flag (Q/

C): Indicates the mode specified by the host

at the end of an SERIRQ transfer cycle (stop frame).

Bit 7

Description

Continuous mode

(Initial value)

[Clearing conditions]

• LPC hardware reset, LPC software reset

• Specification by SERIRQ transfer cycle stop frame

Quiet mode

[Setting condition]

• Specification by SERIRQ transfer cycle stop frame

SIRQCR0 Bit 6—Reserved: This is a readable/writable reserved bit.

SIRQCR0 Bit 5—Interrupt Enable Direct Mode (IEDIR): Specifies whether LPC channel 2

and channel 3 SERIRQ interrupt source (SMI, HIRQ6, HIRQ9 to HIRQ11) generation is

conditional upon OBF, or is controlled only by the host interrupt enable bit.

Bit 5

IEDIR

Description

Host interrupt is requested when host interrupt enable bit and corresponding

OBF are both set to 1

(Initial value)

Host interrupt is requested when host interrupt enable bit is set to 1

HD64F2149YV Folha de dados(PDF) 655 Page - Renesas Technology Corp

HD64F2149YV Folha de dados(HTML) 655 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL